Sram circuitry

ABSTRACT

A static ram cell is described. The cell includes a pair of cross-coupled transistors and a pair of diode-connected transistors operated from a wordline that provides power to the cell. The cell has three main operating modes, reading, writing, and data retention. Reading is performed by sensing current flowing from a powered-up wordline through a conductive one of the cross-coupled transistors. Writing is performed by pulsing the source of the conductive one of the cross-coupled transistors with a positive voltage to flip the conductive states of the cross-coupled transistors. Data retention is performed by using leakage currents to retain the conductive states of the cross-coupled transistors. A decoder for an array of static ram cells may be operated synchronously and in a pipelined fashion using a rotary traveling wave oscillator that provides the clocks for the pipeline. The cell is capable of detecting an alpha particle strike with suitable circuitry.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.11/621,108, filed Jan. 8, 2007, titled SRAM CIRCUITRY, which is adivisional of U.S. patent application Ser. No. 11/123,880, filed May 4,2005, titled “SRAM CIRCUITRY,” which claims priority to and incorporatesby reference into the instant application Great Britain Applicationtitled “SRAM04,” having patent application number GB0409728.3, filed May4, 2004.

FIELD OF THE INVENTION

This invention relates generally to SRAM cells and more particularly toa high speed, low power SRAM cell.

DESCRIPTION OF THE RELATED ART

Leakage current in sub-100 nanometer (nm) VLSI devices is becoming anincreasing problem with each generation. At such a small scale, thetransistors have problems ‘turning off’ (because the threshold voltageVth is reduced, which increases sub-threshold current) and most CMOScircuits including SRAM and static logic will leak current from VDD toGND through P- and N-channel transistors. These currents are in theorder of 25 nA per transistor pair. With possibly 1 billion transistorson a chip, the amount of power wasted can be large. Sub-thresholdleakage increases dramatically with temperature and supply voltage. Notethat the other, often quoted, leakage mechanism, gate leakage, can besolved with the correct ‘CMOS recipe’ (see Intel process press-releasesdue for introduction 2007, which uses high-K dielectric and metal gate).

Many VLSI chips today are largely comprised of SRAM arrays (60% of chiparea) with the remainder being logic circuits. An SRAM is prone to leakenergy because of its CMOS (Pmos, Nmos) configuration with obviousleakage paths.

Reducing VDD to reduce leakage current in SRAM and itsoptimization/tradeoffs have been an active research topic. Please referto references [1] and [2].

[1] SRAM LEAKAGE SUPPRESSION BY MINIMIZING STANDBY SUPPLY VOLTAGE.PROCEEDINGS ON THE INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN,Huifang Qin, Yu (Kevin) Cao, Dejan Markovic, Andrei Vladimirescu, JanRabaey, IEEE, March, 2004. Web: http://www.gigascale.org/pubs/519.html.

[2] ANALYZING SOFT ERRORS IN LEAKAGE OPTIMIZED SRAM DESIGN, V.Degalahal, N. Vijaykrishnan, M. J. Irwin, 16th International Conferenceon VLSI Design, January 2003. Web:http://www.gigascale.org/pubs/366.html

Modulating VDD of the SRAM to reduce power is a known technique. Seeso-called “Dozy Cache” schemes. See reference [3].

[3] DROWSY CACHES: SIMPLE TECHNIQUES FOR REDUCING LEAKAGE POWER,Krisztián Flautner, ARM Ltd Nam Sung Kim, Steve Martin, David Blaauw,Trevor Mudge, University of Michigan 29th Annual International Symposiumon Computer Architecture 2002, web:http://csdl.computer.org/comp/proceedings/isca/2002/1605/00/16050148abs.htm

BRIEF SUMMARY OF THE INVENTION

An embodiment of the present invention is a static ram cell thatincludes a pair of cross-coupled transistors and a pair ofdiode-connected transistors. Each of the pair of cross-coupledtransistors has a gate node and a channel between a source node anddrain node, where the first transistor of the pair has the drain nodeconnected to the gate node of the second transistor of the pair, and thesecond transistor of the pair has the drain node connected to the gatenode of the first transistor of the pair, the source node of the firsttransistor of the pair being the true bit line and the source node ofthe second transistor of the pair being the complement bit line. Each ofthe pair of diode-connected transistors has a gate node and a channelbetween a source node and drain node, wherein the channel of the firstof the pair of diode-connected transistors is connected between thedrain of the first of the cross-coupled transistors and a word line, andwherein the channel of the second of the pair of diode-connectedtransistors is connected between the drain of the second of thecross-coupled transistors and the word line. The state of the cell isbased on which of the cross-coupled transistors is conductive.

A method in one embodiment of the present invention of reading the cellincludes (i) setting a wordline of the cell to a first referencevoltage, where the wordline provides the current for reading the stateof the cell, the cell having true and complement bit lines, (ii) settinga mode line of true and complement sense amplifiers connected to thetrue and complement bit lines, respectively, of the static ram cell to asecond reference voltage, and (iii) detecting the current flowing in thetrue or complement bit lines of the cell to sense the state of the cell.

A method in one embodiment of the present invention of writing the cellincludes (i) setting a wordline of the static ram cell to a firstreference voltage, where the wordline provides the current for writingdata into the cell, the cell having true and complement bit lines, withthe bit line having a conductive path to the wordline and the complementbit line having a non-conductive path to the wordline, (ii) connectingthe bit line via a first switch and the complement bit line via a secondswitch to a second reference voltage, (iii) pulsing the bit line of thecell to the first reference voltage during a short time interval towrite new data into the cell, such that the complement bit line has aconductive path to the wordline.

A method of retaining data in the cell in one embodiment of the presentinvention includes setting a wordline of the static ram cell to avoltage that provides leakage currents to the cell, the cell having trueand complement bit lines, with the bit line having a conductive path forcarrying the leakage currents from the wordline and the complement bitline having a non-conductive path to the wordline.

The SRAM cells of the present invention have the advantages of (i) beingvery fast, on the order of 100 pS for a read on a 0.18 μm CMOS; (ii)needing no VDD or VSS wires, as retention power is taken from the bitand wordlines; (iii) having low leakage current through supplymodulation; (iv) having small cells, only 4 transistors and 5 activecontacts; (v) capable of being implemented as a fast “all NMOS” cell;(vi) having a low leakage current retention mode; and (vii) beingcoupled with a very fast current-mode sense amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the presentinvention will become better understood with regard to the followingdescription, appended claims, and accompanying drawings where:

FIG. 1 shows an array of SRAM cells;

FIG. 2 shows the basic SRAM one-bit memory cell;

FIG. 3 shows the current-mode sense amplifiers connected to each of thebitlines;

FIG. 4A shows the voltage waveforms in the various modes of operation;

FIG. 4B shows the current waveforms in the various modes of operation;

FIG. 5 shows the relevant current paths and detection circuitry usedwhen a strike event occurs; and

FIG. 6 shows an embodiment of a pipelined decoder in accordance with thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION Array Blocks

Arrays 20 are built up in the X direction 22 to make the memory wider,and in the Y direction 24 by adding more wordlines. The bitlines 22 arecommoned. An array 20 of SRAM cell shown in FIG. 1 together with theWordline drivers and the bitline amplifiers 26 a-d completes an X*Yarray20.

Multiple Blocks

Multiple array blocks would ordinarily be deployed. This helps inseveral ways. It makes redundancy easier to implement on the arraylevel. It makes access time faster on smaller, less capacitive arrays.The circuits in the individual blocks need only be matched to the localCMOS PVT process conditions on that part of the die. It eases matchingrequirements etc.

New SRAM Cell And Drive Circuits

The circuit here aims to give all the benefits associated with the aboveapproaches but in a much simpler way with less overhead in terms of areaand delay. It should be noted that the circuit is drawn using NFETtransistors, although PFETs could be used in place of any/all of thetransistors with the obvious changes of signal polarities required.Also, depletion mode Nfets could be used as could PN diodes andbreakdown diodes as will become obvious from the explanation of how thecircuit works.

FIG. 2 is the basic SRAM 1-bit memory cell 28. It comprises twoback-back transistors 30, 32 as the state element plus two otherdiode-connected NFETs 34, 36 acting as dual-purpose pullup/accesstransistors. Superficially, this is similar to the cell shown in FIG. 8“4T SRAM cell, without VDD” of [2], but the cell of the presentinvention is configured differently and operates in an entirelydifferent way. It has no ground connection at all (suits SOI especially)and the cell has no pass transistors activated by the wordline. Thecross-coupled transistors 30, 32 of the present invention actuallyconnect directly to the bitlines 38, 40. Finally, the wordline driversare different and the bitline detection mode and circuits are different.In the default quiescent operation, lines bit 38 and nbit 40 are held toground, and the word line 42 is held to a zero or positive voltage(which can vary from about 0 volt to full VDD as will be explainedlater).

Sense Amplifiers/Bias

FIG. 3 shows the current-mode sense amplifiers 44 which terminate eachof the bitlines. They serve three purposes. First, they amplify andintegrate the current-pulse signals received during reading of the arrayto make logic-level voltages from the small-signal bitline currents.Second, they provide a current-return path for the leakage/standbycurrent of the array in the Data-retention mode. Third, they help detectalpha-particle or cosmic ray strikes.

Circuit Description

Basically, the sense amplifier circuit operates as a charge integrator.During amplification, (read mode) the bitline is kept at a low impedanceby the coupling capacitor ccupl 46 and the feedback capacitor cint 48around the amplifier formed from inverters (ni1 50, pi1 52), (ni2 54,pi2 56), and (ni3 58, pi3 60). Therefore, the voltage on the bitline(nominally) doesn't change during detection and instead any integratedcurrent from the bitline swings the Q output towards ground.

In the data-retention mode, the MODE signal 62 can be lowered whichkeeps the Fets nsink 64 and nbias 66 slightly on, providing enough sinkcurrent to power the SRAM cells but allowing for a detection of analpha-strike (described later) on either the Q and nQ outputs.

The following comments should be kept in mind.

In the diagram, the two sense amplifiers are both single-ended, butcould be cross-coupled to be a true differential amplifier.

Stage 2 (or other stage) of the inverting amplifier may needgain-reduction (resistive load) to prevent the amplifier fromoscillating due to phase-lag in the amplifier.

VDD of the sense amplifiers are dropped for the data-retention mode(circuitry Not shown).

CMOS circuits are shown, but NMOS only amplifiers are well-known and canyield an entirely NMOS SRAM chip at lower cost than CMOS due to reducednumber of mask layers required.

Signal integrity is expected to be good because the current-modedetection method involves almost no voltage signal switching on thebitlines.

Operating Modes Of The Array

There are four definite modes of operation of the SRAM, selectable on aword-basis: (1) data retention (low leakage); (2) read; (3) write 1; and(4) write 0.

Data Retention Mode

When the word line 42 is raised more than one threshold voltage abovebit 38 and nbit 40 voltage (usually 0 v). Transistors n1pull 34 andn2pull 36 provide a weak pull-up current to the drains of ncross1 30 andncross2 32 and like an ordinary SRAM cell, whichever is the currentstate of the bit is reinforced by the feedback paths of thecross-coupled devices 30, 32. The wordline drivers are able to providethis low voltage (between 0.2 volts . . . 0.8 volts) to retain the stateof the memory at low leakage current between write cycles (and readcycles, which fully recharge the state). In fact, it is the just theimbalance of sub-threshold (leakage) currents in the cross-coupledtransistors (caused by the gate voltage imbalance when the cell waswritten or read) which retains the state, and all transistors are ableto operate in the sub-threshold range. Voltage on the word drive line 42effectively sets the pull-up or even leakage current for the block.

Read Mode

In the read mode, the word line 42 is raised to approximately VDD, andtransistors n1pull 34 and n2pull 36 provide a strong pull-up current tothe drains of ncross1 30 and ncross2 32. During read-mode, the state ofthe bit is determined by monitoring the current flowing into lines bit38 and nbit 40. For a logic 1 stored in the SRAM cell (ncross1 30 isturned on) current flows from word 42 out to bit 38. The other bitlinenbit 40 receives current only if logic 0 had been stored in the cell, sothe two bit line currents are mutually exclusive. When operating in anSRAM array, non-selected wordlines are held at the data-retentionvoltage level. No current therefore flows into the unselected wordlines.Additionally, the transistor common bitline loading from the inactivewordlines does not significantly affect the detected current-signal(current mode detection is at low voltage swing).

Write Mode

In the write mode the bitlines are used to set the state of the memoryelement instead of reading the state. Write mode begins is exactly likea read mode event (and this can be exploited to do read-modify-writeaccess) with word line 42 being raised to approximately VDD and with thebit 38 and nbit 40 lines held low. This ‘powers up’ the bit cell 28 andallows it to be written. Assume for this example that the data currentlyin the cell is a ‘1’ (i.e., ncross1 30 is on, and ncross2 32 is off),and it is desired to change the data to a zero. To do this, the line bit38 is raised high very quickly to VDD whereupon, by virtue of ncross1 30being switched on, it conducts to allow passbit signal to go high. Veryquickly this causes ncross2 32 to turn on, which discharges the gate ofncross1 30 (node Npassbit drops low) turning it off. Once flipped, thefeedback reinforces the state which persists as bit 38 is brought backto 0 v. Note that the bitline used to write the bit of a particularstate is the opposite bitline to that which detects the currentcorresponding to the state. Also note that there is a charge pumpingmechanism whereby the gates of the Nfet rise with the source signalsduring the write operation and this effect could also be exploited forgenerating higher voltage gate signals for hot-electron tunneling typedevices such as Flash memory cells.

Exemplary Waveforms

FIGS. 4A and 4B show the operation of a single-bit cell in a combinationof read, write and data-retention modes.

t=10 nS, writing a “1”t=20 nS, no operation (data-retention mode)t=30 nS, writing a “1”t=40 nS, readingt=50 nS, writing “1”t=60 nS, writing “0”t=70 nS, writing “1”t=80 nS, writing “0”t=90 nS, checking retention of non-selected wordline when writing “1” toanother word.t=100 nS, writing a “1”

Alpha Particle Corruption

Most SRAM circuits are very sensitive to alpha particle or cosmic raycorruption of stored bit values, especially when operating at lowvoltage and low stored capacitance as is typical of sub-100 nm VLSIcircuits. The circuit of the present invention is no different in thisregard and can have the logic state altered by the impact of ionizingradiation. Alpha strikes in the silicon lattice free current carriers(electrons/holes) effectively turning-on transistors which may have beenoff. For a conventional SRAM cell this can be catastrophic and can flipthe bit, i.e., currents induced by the free carriers could flow aroundthe VDD and VSS lines in the cell and could swap the charge polaritieson the back-back inverters. The event would go unnoticed outside of thebit cell until bad data is read back on the next access. The usualmethods of prevention and/or recovery from these Single Event Upset(SEU) errors are well known in the literature, such as Error Detectionand Correction EDAC [4], which rely on things like redundant bitscoupled to Hamming-codes to find and repair one or more errors. Ifneeded, EDAC circuits can be built into the synchronous pipeline of thenew SRAM system (described later) to avoid decreasing throughput, butthere is another possible method of dealing with the problem.

[4] A CLASS OF OPTIMAL MINIMUM ODD-WEIGHT-COLUMN SEC-DED CODES, M. Y.Hsiao, IBM Journal of Research and Development [online] (Vol. 14, No. 4)(July 1970), available from:http://www.research.ibm.com/journal/rd/144/ibmrd1404I.pdf.

Scrubbing

Scrubbing refers to a background task by which an EDAC equippedmultiport (i.e., two possible address/data access port) SRAM array isable to transparently fix memory errors. A separate scrubbing statemachine steps through each memory location and looks at the syndrome [4]bits to find and fix any one-bit error by writing back to the memory.The main processor is largely unaware of the scrubbing process and inall likelihood never sees a bad data bit because of the background‘scrubbing’ process.

Error Detection And Correction Ability

An interesting aspect of the SRAM cell of the present invention is thelack of VDD or VSS supplies and the provision of current sensingmechanisms in the bitlines and wordline (FIGS. 3 and 5). This offers anintriguing possibility of directly detecting for alpha (or other)particle strikes and repairing these directly without the need forredundancy or ECC. Observing the new SRAM cell in the data retentionmode, there should only be a static DC current corresponding to the biascurrent of the cell and with SOI, because of the lack of a substrateconnection, no current can flow in the cell without it involving currentflow between two or more of the three terminals shown in the diagram.The system works as follows. For most of the time, most of the SRAMarrays on a chip are in the data-retention mode. In this mode the cellsare vulnerable to corruption from an alpha-strike because of low cellvoltage and weak pull-up currents. Now, consider an alpha strike ontransistor ncross2 32 while the state of the cell is “1” (ncross1 30 ison, ncross2 32 is off). Current is induced to flow in ncross2 32 and theonly paths it can flow are those shown in FIG. 5. All current flow pathsare detectable externally. Only an additional transient current-sensor70 in the wordline is needed. The alpha strike is then recorded in itsan X and Y position by the latching detectors 72. The Y position isgiven by the corresponding wordline transient detector bit and the Xposition by the location of a differential transient current between thebitlines. Effectively, the alpha strike can be thought of as an“unexpected read” of the SRAM data. By detecting the polarities of thebitline current detectors, the state of the bit before it was corruptedcan be found. Alpha strikes that cause no change in signal polarity,such as strikes to a NFET which it is already on, are of no interest.Strikes on ncross1 30 when it happens to be off (cell state is 0), arerecorded with the opposite polarity on the bitline current detectors.The principle can be extended to strikes on the diode/pullup transistors34, 36. The FLAG output of the latching circuit 72 can directly invoke a“scrubbing” process to reinstate the correct state on the bit whichposition and proper state is known.

Cache Application Of Soft Error Detection

Cache SRAM memory on modern microprocessors contributes to a lack ofreliability [6] and these problems are expected get worse as dimensionsand voltage shrink. For the application of an SRAM memory cache, asimpler but still useful version of the system described previously canexploit the detection of soft errors, but use an existing mechanism todo the correction. In this application, whenever the CPU requests anitem from the cache and where there is a soft-error (FLAG set from theword or bitline decodes (see above)), we can force the return of a“Miss” on the cache, independently of the normal hit/miss flag logic.This forces the memory subsystem to execute a fetch from external DRAM.As is the nature of cache, this data is automatically propagated to thecache SRAM and so the external fetch itself fixes the fault. The errorflags could apply to a single bit, single word or an entire block ofmemory. For example, it is simpler to implement a scheme on a cachewhere a single soft-error anywhere in the block flags that the wholeblock is invalid (not in the cache). This can be done by resetting allthe entries of the cache lookup mapping to the block in which there is asoft error. These bits go back to normal one by one when a new externalfetch occurs for that address. Both the TAG and the RAM banks of thecache can be protected. An error detected in the TAG cache line alsoinvalidates a possible “HIT” caused by that lookup in the TAG.

[6] AN ACCURATE ANALYSIS OF THE EFFECTS OF SOFT ERRORS IN THEINSTRUCTION AND DATA CACHES OF A PIPELINED MICROPROCESSOR, M.Rebaudengo, M. Sonza Reorda, M. Violante, Proceedings, Design,Automation and Test in Europe Conference, 3-7 Mar., 2003, Messe Munich,Germany. Web: http://www.date-conference.com/conference/2003/

Routability on SOC Chips

With the redesign of the SRAM cell and its array according to thepresent invention, we can look at addressing another problem of SOCdesign, which is the fact that SRAM macros cause blockages in therouting layers. SRAMs usually only occupy metal one M1 and metal two M2.Concerns over signal integrity of the sense amplifiers often disallowsrouting over the SRAM on other metal layers, perhaps all the way to M4.It is an aspect of the present invention that we build-in porosity tothe SRAM as far as routing is concerned, because of the reduced use ofwiring (No VDD, VSS needed), and we can rotate SRAM blocks as needed tore-orient with the prevailing routing direction on the layers.

Pipelined Memory Decode Multithreading

Many microprocessors today are multi-threaded, which is a mechanism foravoiding the penalty of large memory or other off-chip latencies. Amulti-threaded machine is a multi-threaded (or multi-tasking) machineand switches threads immediately after issuing an address request foroff-chip memory data which might take many clock cycles to return. Byswitching threads, another thread can be continued whose latency willtypically have been absorbed during that thread's idle time. That is, ifa memory request has stalled the thread, the data should be availablewhen the thread is continued. Conceptually, by switching among thethreads, the microprocessor is kept fully utilized and themulti-threaded application program executes faster than asingle-threaded application which is periodically idle while waiting foroff-chip data.

In practice, the internal memory controller and the external memoryitself can be a bottleneck. For example, if it takes 20 clock cycles tofetch a given data word from external memory, then the maximum number ofmemory requests is 1 per 20 clock cycles of the microprocessor. The codefor each thread can comprise at most 5% external memory references ifthe latency of the memory interface is not to be exposed (this figure isrelaxed when a cache is used, and various levels of internal caches havelower levels of latency).

Pipelined Memory Decoder

A solution to the above problem, without requiring large amounts ofcache memory, is to increase the throughput of the memory system for themulti-threaded microprocessor. Despite increased memory latency, thethroughput can be improved to one random read/write per clock cycle ifthe memory decoder is pipelined [5]. Multiple requests to memorylocations flow down the pipeline in the memory decoder and perhaps take20 clock cycles to ultimately activate the correct Row/Column. But, thepoint to note is that each clock cycle presents a new Row/Column decodeand is able to perform a new random access data read or write. Using asmaller amount of the expensive and area-consuming on-chip cache RAM,similar performance can be achieved. The SRAM circuits describedpreviously are applicable to this technique.

FIG. 6 shows an embodiment of a pipelined decoder in accordance with thepresent invention. Included in the embodiment are a rotary travelingwave oscillator 100, as described in U.S. Pat. No. 6,556,089, which isincorporated by reference into the present application, a number ofpre-decoder sections 106, 108, 110 that include shift register elements102, which receive serial address data, combinational logic, and anumber of pipeline registers 104 that receive the outputs of thepre-decoding sections, and a number of decoders 114 attached to theoutputs of the pipeline registers.

In the example shown in FIG. 6, address lines A0-A5 are decoded. Thereare three pre-decoding stages 106, 108, 110. The first pre-decodingstage 106 receives address bits A0 and A1 from a first shift registerthat is clocked by a certain tap of the rotary clock and decodes allpossible states of A0 and A1. The second pre-decoding stage 108 receivesaddress bits A2 and A3 from a second shift register that is clocked by adifferent tap of the rotary clock and decodes all possible states of A2and A3. The third pre-decoding stage 110 receives address bits A4 and A5from a third shift register that is clocked yet another different tap ofthe rotary clock and decodes all possible states of A4 and A5.

The four outputs of the first, second, and third pre-decoding stages areeach captured in a set of pipeline registers 104 whose clocks areconnected to taps of the rotary clock. The twelve outputs of thepipeline registers form a pre-decode bus 116 to which connections can bemade to complete the decoding. Note that as the traveling wave CLK andCLK* move about the rotary clock loop, say in the clockwise direction,the first, second and third shift registers are clocked, and then thepipeline registers of the third, second and first pre-coding stages areclocked. Thus, each pre-decoding stage is pipelined as between the shiftregister and the pipeline registers and each pre-decoding stage ispipeline with respect to the other pre-decoding stages.

[5] PIPELINE MEMORY DECODERS. EXPLORING HIGH BANDWIDTH PIPELINED CACHEARCHITECTURE FOR SCALED TECHNOLOGY [p. 778] A. Agarwal, T. Vijaykumar,and K. Roy, Proceedings, Design, Automation and Test in EuropeConference, 3-7 Mar., 2003, Messe Munich, Germany. Web:http://www.date-conference.com/conference/2003/

Multiport SRAM, SERDES

SRAMS are often designed to be multi-port, meaning there are twoseparate address accesses to the same bit-storage nodes. Anothertechnique to achieve the same effect is to multiplex the address anddata lines of the SRAM between two or more ports and time-share accessto the RAM. This eliminates contention between the ports but requireshigher speed for the SRAM.

An interesting possibility where the address decoder is pipelined is touse SERDES ports to multiplex the address and data from multiple remotesources at the 1-bit level and feed the bits alternately from eachSERDES address receiver port into the pipeline stages. Having addressand data as the single-bit streams allows easy arithmetic on the addressand data operands and could be use for memory management purposes.

Although the present invention has been described in considerable detailwith reference to certain preferred versions thereof, other versions arepossible. Therefore, the spirit and scope of the appended claims shouldnot be limited to the description of the preferred versions containedherein.

1. A method for writing data into a static ram cell, the methodcomprising: setting a wordline of the static ram cell to a firstreference voltage, the wordline providing the current for writing datainto the cell, the cell having true and complement bit lines, the bitline having a conductive path to the wordline and the complement bitline having a non-conductive path to the wordline; connecting the bitline via a first switch and the complement bit line via a second switchto a second reference voltage; and pulsing the bit line of the cell tothe first reference voltage during a short time interval to write newdata into the cell, such that the complement bit line has a conductivepath to the wordline.
 2. A method for retaining data in a static ramcell, the method comprising setting a wordline of the static ram cell toa voltage that provides leakage currents to the cell, the cell havingtrue and complement bit lines, the bit line having a conductive path forcarrying the leakage currents from the wordline and the complement bitline having a non-conductive path to the wordline.
 3. A method forretaining data in a static ram cell as recited in claim 2, wherein thetrue and complement bit lines have been set to a particular voltage; andwherein the voltage of the wordline is more than one threshold voltageabove the particular voltage on the true and complement bit lines.
 4. Amethod for retaining data in a static ram cell as recited in claim 2,further comprising detecting current flow in the non-conductive path tothe wordline; and recording the detected current flow in a latchingdetector, the latching detector indicating a strike event at the cell.